Hardware: central processing unit (CPU) architecture, components and their functions (ALU, CU, registers, buses, cache)

What you'll learn

This revision guide covers the architecture of the central processing unit (CPU) and how its components work together to execute instructions. You'll understand the purpose of the ALU, Control Unit, registers, buses and cache memory, and how they interact during the fetch-decode-execute cycle. This topic is fundamental to understanding how computers process data and is frequently tested in both Paper 1 and Paper 2 of the CIE IGCSE Computer Science examination.

Key terms and definitions

Central Processing Unit (CPU) — the electronic circuitry that executes instructions from programs by performing basic arithmetic, logic, control and input/output operations

Arithmetic Logic Unit (ALU) — the component of the CPU that performs arithmetic operations (addition, subtraction) and logical operations (AND, OR, NOT, comparisons)

Control Unit (CU) — the component that manages the execution of instructions by directing the operation of the processor, controlling the flow of data between the CPU and other devices

Register — a small, high-speed storage location within the CPU used to temporarily hold data, addresses or instructions during processing

System bus — a set of parallel wires that transmits data, addresses and control signals between the CPU and other components

Cache memory — a small amount of high-speed memory located inside or very close to the CPU that stores frequently accessed data and instructions

Clock speed — the number of fetch-decode-execute cycles the CPU can complete per second, measured in hertz (Hz)

Core — an independent processing unit within a CPU capable of executing its own fetch-decode-execute cycle

Core concepts

CPU architecture overview

The CPU is the 'brain' of the computer system. It consists of several key components that work together to process instructions:

• The Arithmetic Logic Unit (ALU) performs all calculations and logical decisions
• The Control Unit (CU) coordinates and manages all CPU operations
• Registers provide temporary, high-speed storage for data being processed
• The system buses transport data between components
• Cache memory stores frequently used instructions and data for rapid access

These components are all housed on a single integrated circuit chip called a microprocessor. In modern systems, the CPU may contain multiple cores, each capable of independent processing.

The Arithmetic Logic Unit (ALU)

The ALU performs two categories of operations:

Arithmetic operations:

• Addition and subtraction
• Multiplication and division (in some processors)
• Increment and decrement operations

Logical operations:

• Boolean logic (AND, OR, NOT, XOR)
• Comparison operations (equal to, greater than, less than)
• Bit-shifting operations

The ALU receives data from registers, performs the requested operation, and stores the result back in a register. It uses logic gates to perform these operations and sets flags to indicate conditions such as zero results, negative numbers or overflow errors.

The Control Unit (CU)

The Control Unit manages and coordinates all operations within the CPU. Its responsibilities include:

• Controlling the fetch-decode-execute cycle
• Decoding instructions to determine what operations are required
• Sending control signals to other components (ALU, registers, memory)
• Managing the timing of operations using the system clock
• Directing data flow between the CPU and other system components

The CU does not process or store data itself. Instead, it acts as a 'traffic controller', ensuring that instructions are executed in the correct sequence and that data moves to the right locations at the right time.

Registers

Registers are small storage locations within the CPU that hold data temporarily during processing. They are the fastest form of memory in the computer system. Key registers in the CIE IGCSE specification include:

Program Counter (PC):

• Holds the memory address of the next instruction to be fetched
• Automatically increments after each instruction is fetched
• Can be changed by jump or branch instructions

Memory Address Register (MAR):

• Holds the address of the memory location to be read from or written to
• Connected to the address bus

Memory Data Register (MDR):

• Temporarily stores data being transferred to or from memory
• Connected to the data bus
• Also called the Memory Buffer Register (MBR)

Current Instruction Register (CIR):

• Holds the instruction currently being decoded and executed
• Also called the Instruction Register (IR)

Accumulator (ACC):

• Stores the results of calculations performed by the ALU
• Holds intermediate results during processing
• One of the most frequently used registers

System buses

The system bus is a collection of parallel wires that carries data between the CPU and other system components. It consists of three separate buses:

Data bus:

• Carries data between the CPU, memory and I/O devices
• Bi-directional (data can flow in both directions)
• Width typically 32 or 64 bits in modern systems
• A wider data bus allows more data to be transferred simultaneously

Address bus:

• Carries memory addresses from the CPU to memory and I/O devices
• Uni-directional (addresses only flow from the CPU)
• Width determines the maximum addressable memory (e.g., 32-bit address bus can address 2³² memory locations)

Control bus:

• Carries control signals that manage and coordinate system operations
• Bi-directional
• Signals include: memory read, memory write, clock signals, interrupt requests, bus requests

The three buses work together during memory operations. For example, when reading from memory: the address travels on the address bus, the control bus carries the 'read' signal, and the requested data returns on the data bus.

Cache memory

Cache memory is a small amount of very fast memory located on or near the CPU chip. It bridges the speed gap between the fast CPU and slower main memory (RAM).

How cache works:

1. When the CPU needs data, it first checks the cache
2. If the data is present (a 'cache hit'), it's retrieved quickly
3. If the data is not present (a 'cache miss'), it must be fetched from RAM
4. Frequently accessed data and instructions are copied to cache for future use

Levels of cache:

• Level 1 (L1) cache: Smallest and fastest, typically 32-64 KB per core
• Level 2 (L2) cache: Larger but slightly slower, typically 256 KB-1 MB per core
• Level 3 (L3) cache: Largest and slowest cache level, typically several MB shared between cores

Cache significantly improves system performance because the CPU can access cached data in 1-2 clock cycles compared to 50-200 cycles for RAM access.

The fetch-decode-execute cycle

The CPU processes instructions through a continuous three-stage cycle:

Fetch stage:

1. Address from the Program Counter is copied to the MAR
2. The instruction at that address is fetched from memory via the data bus
3. The instruction is copied into the MDR
4. The instruction moves from MDR to the CIR
5. The Program Counter increments to point to the next instruction

Decode stage:

1. The Control Unit decodes the instruction held in the CIR
2. The instruction is split into opcode (operation) and operand (data/address)
3. The CU determines what operation is required and what data is needed

Execute stage:

1. The Control Unit sends control signals to appropriate components
2. If required, the ALU performs calculations or logical operations
3. Results are stored in registers or written back to memory
4. The cycle then repeats for the next instruction

This cycle repeats billions of times per second, with the rate determined by the CPU's clock speed. A CPU with a clock speed of 3.5 GHz completes 3.5 billion cycles per second.

Factors affecting CPU performance

Clock speed:

• Measured in gigahertz (GHz)
• Higher clock speeds mean more instructions processed per second
• Increasing clock speed generates more heat and requires more power

Number of cores:

• Each core can execute its own fetch-decode-execute cycle independently
• Multi-core processors can run multiple programs or threads simultaneously
• Not all software can effectively utilize multiple cores

Cache size:

• Larger cache stores more frequently accessed data
• Reduces the number of slower RAM accesses required
• L1, L2 and L3 caches offer different capacity/speed trade-offs

Worked examples

Example 1: Describing the role of CPU components

Question: Describe the role of the Arithmetic Logic Unit (ALU) and give two examples of operations it performs. [4 marks]

Mark scheme answer:

The ALU performs arithmetic operations [1 mark] and logical operations [1 mark].

Examples of operations (any two for 1 mark each):

• Addition/subtraction
• Multiplication/division
• Comparison operations (greater than, equal to, less than)
• Boolean logic (AND, OR, NOT)

Example 2: Explaining registers and buses

Question: A CPU needs to fetch an instruction from memory.

(a) Name the register that holds the address of this instruction. [1 mark]

(b) Explain how the three buses are used during the fetch stage. [6 marks]

Mark scheme answer:

(a) Program Counter (PC) [1 mark] or Memory Address Register (MAR) [1 mark]

(b)

• The address from the Program Counter is placed on the address bus [1 mark]
• The address bus carries this address to main memory [1 mark]
• The control bus carries a 'read' signal [1 mark] to indicate a memory read operation is required [1 mark]
• The data bus carries the instruction from memory [1 mark] back to the CPU/MDR [1 mark]

[Award maximum 6 marks]

Example 3: Cache memory

Question: Explain why cache memory improves the performance of a computer system. [3 marks]

Mark scheme answer:

• Cache is much faster than RAM/main memory [1 mark]
• Frequently accessed data/instructions are stored in cache [1 mark]
• The CPU can access this data more quickly, reducing wait time [1 mark] / fewer accesses to slower RAM are needed [1 mark]

[Award maximum 3 marks]

Common mistakes and how to avoid them

• Confusing the roles of MAR and MDR: Remember that MAR holds addresses (where to read/write) while MDR holds actual data (what to read/write). The MAR connects to the address bus; the MDR connects to the data bus.

• Stating that the ALU 'stores' data: The ALU performs operations on data but doesn't store it. Results are stored in registers (typically the accumulator). Always distinguish between processing and storage.

• Saying cache is 'a type of RAM': While both are memory, cache is specifically high-speed memory located on or very close to the CPU. It has different technology, location and purpose compared to main memory.

• Mixing up clock speed and number of cores: These are separate factors affecting performance. A 4-core CPU at 2 GHz is different from a 2-core CPU at 4 GHz. Both factors matter, but in different ways depending on the workload.

• Incomplete fetch-decode-execute cycle descriptions: Many students omit key details like incrementing the Program Counter or the role of specific registers. Practice writing complete, step-by-step descriptions that include register names.

• Forgetting that the control bus is bi-directional: While the address bus is uni-directional and the data bus is bi-directional, students often incorrectly assume the control bus only carries signals from the CPU outward. It also receives interrupt requests and other signals from devices.

Exam technique for "Hardware: central processing unit (CPU) architecture, components and their functions (ALU, CU, registers, buses, cache)"

• Command words matter: 'Describe' requires you to state features or characteristics; 'Explain' requires reasons or causes. For a 'describe' question about the ALU, state what it does. For an 'explain' question, describe what it does and why this matters.

• Use specific register names: Generic answers like "the register" lose marks. Use precise terminology: Program Counter, Memory Address Register, Memory Data Register, Current Instruction Register, Accumulator. The specification requires you to know these specific registers.

• Structure fetch-decode-execute answers carefully: Use numbered steps or clear paragraphs for each stage. Include: which registers are involved, what data moves where, and the role of each bus. A well-structured answer is easier to mark and less likely to miss steps.

• Relate performance factors to real improvements: When explaining how cache, clock speed or cores improve performance, connect them to measurable outcomes: "reduces time taken," "processes more instructions per second," or "allows multiple programs to run simultaneously." Vague statements like "makes the computer faster" earn fewer marks.

Quick revision summary

The CPU executes instructions through its key components: the ALU performs calculations and logic operations; the Control Unit coordinates all CPU activities; registers provide high-speed temporary storage (PC, MAR, MDR, CIR, ACC). The system buses (data, address, control) transport information between components. Cache memory stores frequently accessed data for rapid retrieval, significantly improving performance. The CPU continuously repeats the fetch-decode-execute cycle, with performance determined by clock speed, number of cores and cache size.